Experience: 5 Years
Job Overview
We are seeking a highly motivated RTL Engineer to contribute to the design and implementation of cutting-edge Networking ICs focused on AI Networking. This role offers a unique opportunity to architect, design, and productize advanced high-speed networking devices that will shape the future of networking technology.
Key Responsibilities
- Architect and design solutions for high-speed networking devices, focusing on latency optimization, memory management, and Quality of Service (QoS) support.
- Implement RTL designs on ASIC platforms ensuring compliance with industry standards and rigorous performance benchmarks.
- Conduct thorough testing, validation, and debugging to guarantee functionality, reliability, and performance of the networking IC.
- Analyze and optimize memory and buffering subsystems to enhance overall performance metrics.
- Provide support for networking protocols and standards, especially related to input/output queues and Ethernet protocols.
- Collaborate closely with cross-functional teams including hardware engineers, firmware developers, and system architects to troubleshoot and resolve complex packet queuing and networking issues.
Required Skills & Qualifications
- Strong proficiency in SystemVerilog and Verilog with proven experience in RTL design and ownership of memory subsystems.
- Expertise in designing and optimizing memory algorithms and QoS mechanisms for high-speed networking devices.
- Solid understanding of ASIC design methodologies, including RTL simulation and verification using tools such as Synopsys and Cadence.
- Experience with Ethernet and PCIe networking protocols and related verification methodologies.
- Excellent analytical and problem-solving skills with meticulous attention to detail in debugging complex networking issues.
- Strong communication skills to effectively collaborate in a team environment and present technical concepts clearly to diverse stakeholders.
Application
Please send your CV to hr@nyxses.com